
ST72321xx-Auto PWM auto-reload timer (ART)
Doc ID 13829 Rev 1 95/243
12.3.4 PWM control register (PWMCR)
Table 49. PWM frequency versus resolution
ARTARR value Resolution
f
PWM
Min Max
0 8-bit ~0.244 kHz 31.25 kHz
[ 0..127 ] > 7-bit ~0.244 kHz 62.5 kHz
[ 128..191 ] > 6-bit ~0.488 kHz 125 kHz
[ 192..223 ] > 5-bit ~0.977 kHz 250 kHz
[ 224..239 ] > 4-bit ~1.953 kHz 500 kHz
PWMCR Reset value: 0000 0000 (00h)
76543210
OE[3:0] OP[3:0]
RW RW
Table 50. PWMCR register description
Bit Name Function
7:4 OE[3:0]
PWM Output Enable
These bits are set and cleared by software. They enable or disable the PWM
output channels independently acting on the corresponding I/O pin.
0: PWM output disabled
1: PWM output enabled
3:0 OP[3:0]
PWM Output Polarity
These bits are set and cleared by software. They independently select the polarity
of the four PWM output signals (see Ta bl e 51 ).
Table 51. PWM output signal polarity selection
PWMx output level
OPx
(1)
1. When an OPx bit is modified, the PWMx output signal polarity is immediately reversed.
Counter <= OCRx Counter > OCRx
100
011
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