Auto Page CPX-3600 Specifikace stáhnout pdf (Strana 115)

ST72321xx-Auto 16-bit timer

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13.7.3 Control/status register (CSR)

5OPM

One Pulse Mode

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the

OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the

generated pulse depends on the contents of the OC1R register.

4PWM

Pulse Width Modulation

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the

length of the pulse depends on the value of OC1R register; the period depends on

the value of OC2R register.

3:2 CC[1:0]

Clock Control

The timer clock mode depends on these bits (see Ta bl e 6 1).

1IEDG2

Input Edge 2

This bit determines which type of level transition on the ICAP2 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

0 EXEDG

External Clock Edge

This bit determines which type of level transition on the external clock pin EXTCLK

will trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

Table 61. Timer clock selection

Timer clock CC1 CC0

CPU

/ 4 0 0

CPU

/ 2 0 1

CPU

/ 8 1 0

External clock (where available)

(1)

1. If the external clock pin is not available, programming the external clock configuration stops the counter.

Table 60. CR2 register description (continued)

Bit Name Function

CSR Reset value: xxxx x0xx (xxh)

76543210

ICF1 OCF1 TOF ICF2 OCF2 TIMD Reserved

RO RO RO RO RO RW -

1 2 ... 110 111 112 113 114 115 116 117 118 119 120 ... 242 243

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