
ST72321xx-Auto Electrical characteristics
Doc ID 13829 Rev 1 213/243
Figure 95. SPI master timing diagram
(1)
1. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
SS
INPUT
SCK
INPUT
CPHA = 0
MOSI
OUTPUT
MISO
INPUT
CPHA = 0
CPHA = 1
CPHA = 1
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
h(MI)
t
su(MI)
MSB IN
MSB OUT
BIT6 IN
BIT6 OUT
LSB OUT
LSB IN
See note 2 See note 2
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
t
r(SCK)
t
f(SCK)
t
h(MO)
t
v(MO)
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