Auto Page CPX-3600 Specifikace stáhnout pdf (Strana 157)

ST72321xx-Auto I2C bus interface (I2C)

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16.3.3 SDA/SCL line control

Transmitter mode

The interface holds the clock line low before transmission to wait for the microcontroller to

write the byte in the data register.

Receiver mode

The interface holds the clock line low after reception to wait for the microcontroller to read

the byte in the data register.

The SCL frequency (f

SCL

) is controlled by a programmable clock divider which depends on

the I

C bus mode.

When the I

C cell is enabled, the SDA and SCL ports must be configured as floating inputs.

In this case, the value of the external pull-up resistor used depends on the application.

When the I

C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.

Figure 67. I

C interface block diagram

DATA REGISTER (DR)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGISTER 1 (OAR1)

CLOCK CONTROL REGISTER (CCR)

STATUS REGISTER 1 (SR1)

CONTROL REGISTER (CR)

CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

CLOCK CONTROL

DATA CONTROL

SCL or SCLI

SDA or SDAI

OWN ADDRESS REGISTER 2 (OAR2)

1 2 ... 152 153 154 155 156 157 158 159 160 161 162 ... 242 243

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