
Interrupts ST72321xx-Auto
56/243 Doc ID 13829 Rev 1
Table 20. Interrupt mapping
No.
Source
block
Description
Register
label
Priority
order
Exit
from
Halt
(1)
Address
vector
RESET Reset
N/A
yes FFFEh-FFFFh
TRAP Software interrupt no FFFCh-FFFDh
0 TLI External top level interrupt EICR yes FFFAh-FFFBh
1 MCC/RTC Main clock controller time base interrupt MCCSR
Higher
priority
yes FFF8h-FFF9h
2 ei0 External interrupt port A3..0
N/A
yes FFF6h-FFF7h
3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h
4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h
5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h
6 Not used FFEEh-FFEFh
7 SPI SPI peripheral interrupts SPICSR yes
(2)
FFECh-FFEDh
8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh
9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h
10 SCI SCI peripheral interrupts SCISR
Lower
priority
no FFE6h-FFE7h
11 AVD Auxiliary voltage detector interrupt SICSR no FFE4h-FFE5h
12 I2C I2C peripheral interrupts
(see
peripheral)
no FFE2h-FFE3h
13 PWM ART PWM ART interrupt ARTCSR yes
(3)
FFE0h-FFE1h
1. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.
2. Exit from HALT possible when SPI is in slave mode.
3. Exit from HALT possible when PWM ART is in external clock mode.
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