
ST72321xx-Auto Supply, reset and clock management
Doc ID 13829 Rev 1 45/243
Figure 15. Using the AVD to monitor V
DD
(AVDS bit = 0)
Monitoring a voltage on the EVD pin
This mode is selected by setting the AVDS bit in the SICSR register.
The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set.
This interrupt is generated on the rising and falling edges of the comparator output. This
means it is generated when either one of these two events occur:
● V
EVD
rises up to V
IT+(EVD)
●
V
EVD
falls down to V
IT-(EVD)
The EVD function is illustrated in Figure 16.
For more details, refer to Section 19: Electrical characteristics.
V
DD
V
IT+(AVD)
V
IT-(AVD)
AVDF bit 0 0RESET VALUE
IF AVDIE bit = 1
V
hyst
AVD INTERRUPT
REQUEST
INTERRUPT PROCESS
INTERRUPT PROCESS
V
IT+(LVD)
V
IT-(LVD)
LVD RESET
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
1
1
t
rv
VOLTAGE RISE TIME
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