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ST72321xx-Auto I/O ports
Doc ID 13829 Rev 1 75/243
9.4 Low power modes
9.5 Interrupts
The external interrupt event generates an interrupt if the corresponding configuration is
selected with DDR and OR registers and the interrupt mask in the CC register is not active
(RIM instruction).
Port B
PB7, PB3 floating floating interrupt open-drain push-pull
PB6:5, PB4, PB2:0 floating pull-up interrupt open-drain push-pull
Port C PC7:0 floating pull-up open-drain push-pull
Port D PD7:0 floating pull-up open-drain push-pull
Port E
PE7:3, PE1:0 floating pull-up open drain push-pull
PE2 (Flash devices) pull-up input only
PE2 (ROM devices) floating open drain push-pull
Port F
PF7:3 floating pull-up open-drain push-pull
PF2 floating floating interrupt open-drain push-pull
PF1:0 floating pull-up interrupt open-drain push-pull
Table 31. I/O port configuration (continued)
Port Pin name
Input (DDR = 0) Output (DDR = 1)
OR = 0 OR = 1 OR = 0 OR = 1
Table 32. Effect of low power modes on I/O ports
Mode Effect
Wait No effect on I/O ports. External interrupts cause the device to exit from Wait mode.
Halt No effect on I/O ports. External interrupts cause the device to exit from Halt mode.
Table 33. I/O port interrupt control/wake-up capability
Interrupt event Event flag
Enable
control bit
Exit from
Wait
Exit from
Halt
External interrupt on selected
external event
- DDRx, ORx Yes Yes
Table 34. I/O port register map and reset values
Address (Hex.)Register label76543210
Reset value of all I/O port registers00000000
0000h PADR
MSB LSB0001h PADDR
0002h PAOR
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