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ST72321xx-Auto Serial peripheral interface (SPI)
Doc ID 13829 Rev 1 133/243
14.8.3 Data I/O register (SPIDR)
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
4MODF
Mode Fault flag
This bit is set by hardware when the SS
pin is pulled low in master mode (see
Master mode fault (MODF) on page 128). An SPI interrupt can be generated if
SPIE = 1 in the SPICSR register. This bit is cleared by a software sequence (An
access to the SPICR register while MODF = 1 followed by a write to the SPICR
register).
0: No master mode fault detected
1: A fault in master mode has been detected
3 - Reserved, must be kept cleared
2SOD
SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
1 SSM
SS
Management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS
pin and uses the SSI bit value instead. See Slave select management on
page 123.
0: Hardware management (SS
managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin
free for general-purpose I/O)
0 SSI
SS
Internal Mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the
level of the SS
slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
Table 68. SPICSR register description (continued)
Bit Name Function
SPIDR Reset value: Undefined
76543210
D[7:0]
RW
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