Figure 59. Data clock timing diagram
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
CAPTURE STROBE
CPHA = 1
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit
CAPTURE STROBE
CPHA = 0
Note: This figure should not be used as a replacement for parametric information.
Refer to Section 19: Electrical characteristics.
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
SS
(to slave)
Komentáře k této Příručce