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Supply, reset and clock management ST72321xx-Auto
38/243 Doc ID 13829 Rev 1
6.3 Phase locked loop
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
OSC2
of 4 to 8 MHz. The PLL is enabled by option
byte. If the PLL is disabled, then f
OSC2
=f
OSC
/2.
Caution: The PLL is not recommended for applications where timing accuracy is required (see
Section 19.5.5: PLL characteristics on page 198).
Figure 10. PLL block diagram
6.4 Multi-oscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multi-oscillator block:
an external source
4 crystal or ceramic resonator oscillators
an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 10. Refer to Section 19: Electrical characteristics for more details.
Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
f
OSC
clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an
unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
0
1
PLL OPTION BIT
PLL x 2
f
OSC2
/ 2
f
OSC
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