
10-bit A/D converter (ADC) ST72321xx-Auto
174/243 Doc ID 13829 Rev 1
17.3.3 Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
17.4 Low power modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
17.5 Interrupts
None.
17.6 ADC registers
17.6.1 Control/status register (ADCCSR)
Table 91. Effect of low power modes on ADC
Mode Effect
Wait No effect on A/D converter
Halt
A/D converter disabled.
After wake-up from Halt mode, the A/D converter requires a stabilization time t
STAB
(see
Section 19: Electrical characteristics) before accurate conversions can be performed.
ADCCSR Reset value: 0000 0000 (00h)
76 543210
EOC SPEED ADON Reserved CH[3:0]
RO RW RW - RW
Table 92. ADCCSR register description
Bit Name Function
7EOC
End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the
ADCDRH register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
6 SPEED
ADC clock selection
This bit is set and cleared by software.
0: f
ADC
= f
CPU
/4
1: f
ADC
= f
CPU
/2
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