
ST72321xx-Auto Serial peripheral interface (SPI)
Doc ID 13829 Rev 1 131/243
14.8 SPI registers
14.8.1 Control register (SPICR)
SPICR Reset value: 0000 xxxx (0xh)
76543210
SPIE SPE SPR2 MSTR CPOL CPHA SPR[1:0]
RW RW RW RW RW RW RW
Table 66. SPICR register description
Bit Name Function
7SPIE
Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
6 SPE
Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS
= 0 (see Master mode fault (MODF) on page 128). The SPE bit
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
5SPR2
Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Tabl e 67 .
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
4MSTR
Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS
=0 (see Master mode fault (MODF) on page 128).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
3CPOL
Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
2CPHA
Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
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