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ST72321xx-Auto Serial peripheral interface (SPI)
Doc ID 13829 Rev 1 129/243
Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence
14.5.4 Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see Figure 61).
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS
pins of the slave devices.
The SS
pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 61. Single master / multiple slave configuration
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
Read SPIDR
2nd Step
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
WCOL = 0
Read SPICSR
Read SPIDR
Note: Writing to the SPIDR register
instead of reading it does not reset the
WCOL bit.
RESULT
RESULT
MISO
MOSI
MOSI
MOSI MOSI MOSIMISO MISO MISOMISO
SS
SS
SS
SS
SS
SCK SCK
SCK
SCK
SCK
5V
Ports
Slave
MCU
Slave
MCU
Slave
MCU
Slave
MCU
Master
MCU
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