
Serial peripheral interface (SPI) ST72321xx-Auto
122/243 Doc ID 13829 Rev 1
Figure 55. Serial peripheral interface block diagram
14.3.1 Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 56.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 59) but master and
slave must be programmed with the same timing mode.
SPIDR
Read Buffer
8-bit Shift Register
Write
Read
Data/Address Bus
SPI
SPIE SPE MSTR CPHA SPR0SPR1CPOL
SERIAL CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
STATE
SPICR
SPICSR
Interrupt
request
MASTER
CONTROL
SPR2
07
07
SPIF WCOL MODF 0OVR SSISSMSOD
SOD
bit
SS
1
0
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