
ST72321xx-Auto PWM auto-reload timer (ART)
Doc ID 13829 Rev 1 93/243
12.3 ART registers
12.3.1 Control/status register (ARTCSR)
ARTCSR Reset value: 0000 0000 (00h)
76543210
EXCL CC[2:0] TCE FCRL OIE OVF
RW RW RW RW RW RW
Table 45. ARTCSR register description
Bit Name Function
7 EXCL
External Clock
This bit is set and cleared by software. It selects the input clock for the 7-bit
prescaler.
0: CPU clock
1: External clock
6:4 CC[2:0]
Counter Clock Control
These bits are set and cleared by software. They determine the prescaler division
ratio from f
INPUT
(see Tabl e 46 ).
3TCE
Timer Counter Enable
This bit is set and cleared by software. It puts the timer in the lowest power
consumption mode.
0: Counter stopped (prescaler and counter frozen)
1: Counter running
2 FCRL
Force Counter Re-Load
This bit is write-only and any attempt to read it will yield a logical zero. When set, it
causes the contents of ARTARR register to be loaded into the counter, and the
content of the prescaler register to be cleared in order to initialize the timer before
starting to count.
1OIE
Overflow Interrupt Enable
This bit is set and cleared by software. It allows to enable/disable the interrupt which
is generated when the OVF bit is set.
0: Overflow Interrupt disable
1: Overflow Interrupt enable
0OVF
Overflow Flag
This bit is set by hardware and cleared by software reading the ARTCSR register. It
indicates the transition of the counter from FFh to the ARTARR value.
0: New transition not yet reached
1: Transition reached
Table 46. Prescaler selection for ART
f
COUNTER
With f
INPUT
= 8 MHz CC2 CC1 CC0
f
INPUT
8 MHz 000
f
INPUT
/ 2 4 MHz 0 0 1
f
INPUT
/ 4 2 MHz 0 1 0
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