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ST72321xx-Auto Serial communications interface (SCI)

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15.7.4 Data register (SCIDR)

This register contains the Received or Transmitted data character, depending on whether it

is read from or written to.

The Data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 62).

The RDR register provides the parallel interface between the input shift register and the

internal bus (see Figure 62).

15.7.5 Baud rate register (SCIBRR)

2RE

Receiver enable

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

1RWU

Receiver wake-up

This bit determines if the SCI is in mute mode or not. It is set and cleared by software

and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the RWU bit), the SCI must receive some

data first, otherwise it cannot function in Mute mode with wake-up by idle line

detection.

0 SBK

Send break

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter sends a BREAK word

at the end of the current word.

Table 75. SCICR2 register description (continued)

Bit Name Function

SCIDR Reset value: Undefined

76543210

DR[7:0]

SCIBRR Reset value: 0000 0000 (00h)

76543210

SCP[1:0] SCT[2:0] SCR[2:0]

RW RW RW

1 2 ... 146 147 148 149 150 151 152 153 154 155 156 ... 242 243

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