
ST72321xx-Auto Supply, reset and clock management
Doc ID 13829 Rev 1 47/243
6.6.5 System Integrity (SI) Control/Status register (SICSR)
SICSR Reset value: 000x 000x (00h)
76543210
AVDS AVDIE AVDF LVDRF
Reserved
WDGRF
RW RW RW RW - RW
Table 13. SICSR description
Bit Name Function
7AVDS
Voltage Detection selection
This bit is set and cleared by software. Voltage Detection is available only if the
LVD is enabled by option byte.
0: Voltage detection on V
DD
supply
1: Voltage detection on EVD pin
6
AVDIE
Voltage Detector interrupt enable
This bit is set and cleared by software. It enables an interrupt to be generated
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
5AVDF
Voltage Detector flag
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 15 and to Monitoring the VDD main supply on page 44 for additional
details.
0: V
DD
or V
EVD
over V
IT+(AVD)
threshold
1: V
DD
or V
EVD
under V
IT-(AVD)
threshold
4 LVDRF
LVD reset flag
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See Table 14: Reset
source flags for more details. When the LVD is disabled by OPTION BYTE, the
LVDRF bit value is undefined.
3:1 - Reserved, must be kept cleared.
0 WDGRF
Watchdog reset flag
This bit indicates that the last Reset was generated by the Watchdog peripheral. It
is set by hardware (watchdog reset) and cleared by software (writing zero) or an
LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given in
Ta bl e 1 4 .
Table 14. Reset source flags
Reset sources LVDRF WDGRF
External RESET
pin 0 0
Watchdog 0 1
LVD 1 X
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