
Electrical characteristics ST72321xx-Auto
214/243 Doc ID 13829 Rev 1
19.11.2
I
2
C - inter IC control interface
Subject to general operating conditions for V
DD
,
f
CPU
, and T
A
unless otherwise specified.
Refer to Section 19.8: I/O port pin characteristics for more details on the input/output
alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the
requirements of the standard I2C communication protocol described in the following table.
Table 133. I
2
C control interface characteristics
Symbol Parameter
Standard mode I
2
CFast mode I
2
C
(1)
Unit
Min
(2)
Max
(2)
Min
(2)
Max
(2)
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0
(3)
0
(4)
900
(3)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000
20+0.1C
b
300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300
t
h(STA)
START condition hold time 4.0
0.6
µs
t
su(STA)
Repeated START condition setup time 4.7
t
su(STO)
STOP condition setup time 4.0
t
w(STO:STA)
STOP to START condition time (bus free) 4.7 1.3
C
b
Capacitive load for each bus line 400 400 pF
1. At 4 MHz f
CPU
, maximum I
2
C speed (400 kHz) is not achievable. In this case, maximum I
2
C speed will be approximately
260 kHz.
2.
Data based on standard I
2
C protocol requirement, not tested in production.
3.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL
signal.
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
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