
ST72321xx-Auto Serial peripheral interface (SPI)
Doc ID 13829 Rev 1 123/243
Figure 56. Single master/single slave application
14.3.2 Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 58)
In software management, the external SS
pin is free for other application uses and the
internal SS
signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode
● SS internal must be held high continuously
In Slave mode
There are two cases depending on the data/clock timing relationship (see Figure 57):
If CPHA = 1 (data latched on 2nd clock edge):
● SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS
pin either can be tied to V
SS
, or made free for standard I/O by
managing the SS
function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
If CPHA = 0 (data latched on 1st clock edge):
● SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS
is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see Write collision
error (WCOL) on page 128).
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
8-BIT SHIFT REGISTER
MISO
MOSI
MOSI
MISO
SCK
SCK
SLAVE
MASTER
SS
SS
+5V
MSBit LSBit MSBit LSBit
Not used if SS is managed
by software
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