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ST72321xx-Auto Electrical characteristics
Doc ID 13829 Rev 1 203/243
19.8 I/O port pin characteristics
19.8.1 General characteristics
Subject to general operating conditions for V
DD,
f
OSC
, and T
A
unless otherwise specified.
Table 126. I/O port pin general characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage
(1)
CMOS ports
0.3xV
DD
VV
IH
Input high level voltage
(1)
0.7xV
DD
V
hys
Schmitt trigger voltage hysteresis
(2)
0.7
I
INJ(PIN)
(3)
Injected current on PC6 pin (Flash devices
only)
V
DD
=5V
0+4
mAInjected current on an I/O pin ±4
I
INJ(PIN)
(3)
Total injected current (sum of all I/O and
control pins)
±25
I
L
Input leakage current V
SS
< V
IN
< V
DD
±1
µA
I
S
Static current consumption Floating input mode
(4)
400
R
PU
Weak pull-up equivalent resistor
(5)
V
IN
=V
SS
V
DD
= 5V 50 120 250 k
C
IO
I/O pin capacitance 5 pF
t
f(IO)out
Output high to low level fall time
(1)
C
L
= 50pF
Between 10% and 90%
25
ns
t
r(IO)out
Output low to high level rise time
(1)
25
t
w(IT)in
External interrupt pulse time
(6)
1t
CPU
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the V
IN
maximum must be respected, otherwise refer to I
INJ(PIN)
specification. A
positive injection is induced by V
IN
>V
DD
while a negative injection is induced by V
IN
<V
SS
. Refer to Section 19.2.2:
Current characteristics for more details.
4. Configuration not recommended. All unused pins must be kept at a fixed voltage. This can be done by using the output
mode of the I/O, for example, and leaving the I/O unconnected on the board or by an external pull-up or pull-down resistor
(see Figure 82). Static peak current value taken at a fixed V
IN
value, based on design simulation and technology
characteristics, not tested in production. This value depends on V
DD
and temperature values.
5. The R
PU
pull-up equivalent resistor is based on a resistive transistor (corresponding I
PU
current characteristics described in
Figure 83).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
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