
Supply, reset and clock management ST72321xx-Auto
42/243 Doc ID 13829 Rev 1
6.5.5 Internal watchdog RESET
The RESET sequence generated by an internal Watchdog counter overflow is shown in
Figure 13.
Starting from the Watchdog counter underflow, the device RESET
pin acts as an output that
is pulled low during at least t
w(RSTL)out
.
Figure 13. RESET sequences
V
DD
RUN
RESET PIN
EXTERNAL
WATCHDOG
Active Phase
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
t
w(RSTL)out
RUN
t
h(RSTL)in
Active
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN RUN RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (256 or 4096 T
CPU
)
VECTOR FETCH
t
w(RSTL)out
Phase
Active
Phase
Active
Phase
DELAY
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