
Serial peripheral interface (SPI) ST72321xx-Auto
124/243 Doc ID 13829 Rev 1
Figure 57. Generic SS timing diagram
Figure 58. Hardware/Software slave select management
14.3.3 Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1. Write to the SPICR register:
a) Select the clock frequency by configuring the SPR[2:0] bits.
b) Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 59 shows the four possible configurations.
Note: The slave must have the same CPOL and CPHA settings as the master.
2. Write to the SPICSR register:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS
pin high
for the complete byte transmit sequence.
3. Write to the SPICR register:
Set the MSTR and SPE bits
Note: MSTR and SPE bits remain set only if SS
is high).
IMPORTANT: If the SPICSR register is not written first, the SPICR register setting (MSTR
bit) may not be taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Slave SS
(if CPHA=1)
Byte 1 Byte 2 Byte 3
1
0
SS internal
SSM bit
SSI bit
SS
external pin
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