Auto Page CPX-3600 Specifikace Strana 62

  • Stažení
  • Přidat do mých příruček
  • Tisk
  • Strana
    / 243
  • Tabulka s obsahem
  • KNIHY
  • Hodnocené. / 5. Na základě hodnocení zákazníků
Zobrazit stránku 61
Power saving modes ST72321xx-Auto
62/243 Doc ID 13829 Rev 1
8 Power saving modes
8.1 Introduction
To give a large measure of flexibility to the application in terms of power consumption, four
main power saving modes are implemented in the ST7 (see Figure 22): Slow, Wait (Slow
Wait), Active Halt and Halt.
After a RESET the normal operating mode is selected by default (Run mode). This mode
drives the device (CPU and embedded peripherals) by means of a master clock which is
based on the main oscillator frequency divided or multiplied by 2 (f
OSC2
).
From Run mode, the different power saving modes may be selected by setting the relevant
register bits or by calling the specific ST7 software instruction whose action depends on the
oscillator status.
Figure 22. Power saving mode transitions
8.2 Slow mode
This mode has two targets:
To reduce power consumption by decreasing the internal clock in the device,
To adapt the internal clock frequency (f
CPU
) to the available supply voltage.
Slow mode is controlled by three bits in the MCCSR register: the SMS bit which enables or
disables Slow mode and two CPx bits which select the internal slow frequency (f
CPU
).
In this mode, the master clock frequency (f
OSC2
) can be divided by 2, 4, 8 or 16. The CPU
and peripherals are clocked at this lower frequency (f
CPU
).
Note: Slow Wait mode is activated when entering the Wait mode while the device is already in
Slow mode.
POWER CONSUMPTION
WAIT
SLOW
RUN
ACTIVE HALT
High
Low
SLOW WAIT
HALT
Zobrazit stránku 61
1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 242 243

Komentáře k této Příručce

Žádné komentáře