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16-bit timer ST72321xx-Auto
102/243 Doc ID 13829 Rev 1
13.3.2 External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus, the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 43. Counter timing diagram, internal clock divided by 2
Figure 44. Counter timing diagram, internal clock divided by 4
Figure 45. Counter timing diagram, internal clock divided by 8
Note: The MCU is in reset state when the internal reset signal is high; when it is low the MCU is
running.
CPU CLOCK
FFFD
FFFE FFFF 0000 0001 0002 0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD 0000 0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFC FFFD
0000
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