
I2C bus interface (I2C) ST72321xx-Auto
170/243 Doc ID 13829 Rev 1
16.7.7 I
2
C own address register (OAR2)
Table 88. OAR1 register description
Bit Name
Function
7-bit addressing mode 10-bit addressing mode
7:1 ADD[7:1]
Interface address
These bits define the I
2
C bus address
of the interface. They are not cleared
when the interface is disabled
(PE = 0).
Not applicable
0 ADD0
Address direction bit
This bit is ‘don’t care’, the interface
acknowledges either 0 or 1. It is not
cleared when the interface is disabled
(PE = 0).
Address 01h is always ignored.
7:0 ADD[7:0] Not applicable
Interface address
These are the least significant bits of
the I
2
C bus address of the interface.
They are not cleared when the
interface is disabled (PE = 0).
OAR2 Reset value: 0100 0000 (40h)
76543210
FR[1:0] Reserved ADD[9:8] Reserved
RW - RW -
Table 89. OAR2 register description
Bit Name Function
7:6 FR[1:0]
Frequency bits
These bits are set by software only when the interface is disabled (PE = 0). To
configure the interface to I
2
C specified delays, select the value corresponding to
the CPU frequency f
CPU
.
00: f
CPU
< 6 MHz
01: f
CPU
= 6 to 8 MHz
5:3 - Reserved
2:1 ADD[9:8]
Interface address
These are the most significant bits of the I
2
C bus address of the interface (10-bit
mode only). They are not cleared when the interface is disabled (PE = 0).
0-Reserved
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